This invention relates to electronic systems analysis, and, more particularly, to an apparatus and method for evaluating operation of a circuit.
Various software languages exist that are useful for the conceptual design of integrated circuits. These languages are generally known as hardware description languages and include languages such as Very High Speed Integrated Circuit (VHSIC) Hardware Description Language and Verilog, a language for electronic design and gate level simulation. These languages can be used to emulate the operation of a circuit under test. Alternatively, the circuit under test may be a final product.
Previously, in order to check performance counters on a circuit, the known method was to run a simulation, read out performance counters at the end, and check the values in the counters using a post-simulation analysis. A counter is a circuit or part of a circuit that counts specific events in an electronic system. A performance counter is a counter that can provide performance-related information such as occurrences of a particular transaction or response latency. The method described above does not allow checking of the values during run-time. The method also requires a user to perform a separate verification. Finally, this method is limited to verification of counting the number of times certain events have occurred, while performance counters themselves are able to measure a wider variety of events, such as timing counts between events or data throughput. A necessity exists for a method and apparatus which solves the aforementioned problems.
In one embodiment, the present invention is useful in checking the operation of a circuit. Such a circuit may be a software simulation of a given or proposed circuit. In certain instances this software version of the circuit may be the final product. Alternatively, the software version may be part of the design phase used in developing the circuit. The circuit may also be an actual assemblage of electronic components.
In one embodiment, the invention involves sending one or a sequence of working transactions to a circuit under test that will cause the counter values in the circuit to change and keeping and updating an expected counter value according to the transaction sent. A read transaction is then sent to the circuit, which returns the value of the counters in the circuit under test. The two values, the expected counter value and the actual counter value can then be compared.
In another embodiment, the invention involves independently and simultaneously measuring the amount of time that passes between two discreet events. In this embodiment, the system may measure how long a circuit takes to complete a given transaction. This may be done by beginning an external counter when a transaction is sent to the circuit under test and the circuit under test beginning its own internal counter once it receives that certain transaction. Thus, the external and internal counter may be independent of each other. Once the circuit under test finishes the transaction it stops its own internal counter and sends a return transaction. Upon receipt of the return transaction, the external counter stops. The two counters can then be compared, and although the external counter value will always be greater than the value returned by the internal counter due to latency between the verification system and the circuit under test, a measure of performance is obtained.